1. Technical Field
This disclosure relates to delay locked loop circuits, and more particularly to the delay lines used in delay locked loops.
2. Description of the Related Art
A delay locked loop (DLL) may be implemented using either digital or analog circuits. A typical conventional digital implementation includes a delay line formed using a long series chain of inverters. The delay line may be tapped at many nodes along the chain such as between every other inverter, for example. These taps may be fed into multiplexer. Since there may be a large number of taps, they may be fed into a fairly wide multiplexer that selects the tap, and thus the desired delay. Many of these wide multiplexers are implemented using a hierarchical structure with four or more levels. Accordingly, due to the multi-level hierarchical structure of the multiplexer, the minimum delay of the delay line may be dominated by the multiplexer and unacceptably high. Furthermore, the integrated circuit die area used by conventional delay line structures can be quite large.